|Published (Last):||6 November 2017|
|PDF File Size:||14.70 Mb|
|ePub File Size:||5.50 Mb|
|Price:||Free* [*Free Regsitration Required]|
Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts.
It only takes a minute to sign up. With the 74LS 8 bit parallel out serial shift registers, I'm confused about a few things. In the datasheet page3 on the logic diagram why do they suggest using an active low inverter before the active low pin on the clear line?
Is this for some sort of buffer? My second question is if this is a 8-bit register why on the clear-shift-clear timing diagram page 2 do they have 11 clock pulses?
Would we be limited to 8 clock pulses before the registers are full and 11 clock pulses result in potential loss of data? Once the underlying logic circuit is known, practically any question on the device logic state behaviour can be answered.
And in conjunction with full device voltage and timing specifications, practically all questions on the device behaviour and operation can then be answered.
That's the ideal case. In reality, not all datasheets are of good enough quality. Here, it's a matter of opinion but I've found the various 74xxyy datasheets to be pretty comprehensive most of the time. The 'Typical clear-shift-clear sequences' diagram page 2 shows exactly that. It's not a 'Single 8-bit serial-parallel transfer' diagram. The shift register in this device can shift in any number of bits.
All but the most recent 8 bits will appear on the parallel outputs. The rest would have tipped off the end of Qh. It's not uncommon to daisy-chain the devices to produce more than 8 parallel outputs, with the Qh output of one device connected to the A or B input of the next device.
Some bits would pass through earlier devices on their way to later devices and the diagram makes it clear how each device would behave in that situation. Sign up to join this community. The best answers are voted up and rise to the top. Home Questions Tags Users Unanswered. Question about 74LS 8-bit serial in parallel out shift register Ask Question. Asked 5 months ago. Active 5 months ago. Viewed 82 times. Are you sure you linked the correct data sheet because I can't see the timing diagram you mentioned either?
Is there a general purpose for the using that type inverter before an active low on the clear? Isn't the signal just being inverted back to the original? Active Oldest Votes. So there's more for that diagram to show than just a single byte transfer. TonyM TonyM 9, 1 1 gold badge 19 19 silver badges 35 35 bronze badges. Sign up or log in Sign up using Google. Sign up using Facebook.
Our standard product range covers a wide temperature range with long term availability and no mask changes guaranteed. Matching of die size, wire-bond configuration and like-for-like electrical performance delivers a qualified long term die solution. Suitable for low-to-medium volume or hi-rel applications. We combine technical requirement with project economics for a viable die solution.
74LS164 PDF Datasheet浏览和下载
Bare Die Data Sheet: 74LS164
74LS164 Datasheet PDF